Integrated circuits (ICs) are tested and characterized at different points during the manufacturing process by which they are fabricated and assembled, and ultimately shipped to customers. The test and characterization data can be used to grade the performance of the ICs, and to eliminate ICs that fail to meet performance standards set by a manufacturer. The manufacturer can specify minimum requirements for functionality of the IC, and for speed, power, voltage, current, and any other performance-related parameters. ICs that fail to meet any or all of such requirements can be eliminated.
One set of tests is performed at “wafer sort.” At this point, the ICs are fully formed, but have not yet been “diced,” or separated into individual chips. ICs are typically produced on silicon wafers, each wafer having many ICs. During wafer sort, a probe card is used to provide test signals to the IC and receive test results from the IC. The probe card touches down on certain input/output (I/O) bonding pads, and sends and receives signals through those contact points. The test results are analyzed, and the ICs that fail to meet the required performance standards can be discarded when the wafer is diced.
After the ICs are cut from the wafer and separated from each other, the ICs that failed the wafer sort test are eliminated, and the remaining ICs are assembled into their packages. The assembly process can involve, for example, attaching bond wires or solder bumps to the I/O bonding pads of the IC, connecting the IC to a substrate, and enclosing the IC in a protective package. Once assembly is complete, another set of tests, commonly referred to as “final test,” is performed. At final test, automated test equipment (ATE) tests the performance of the fully assembled ICs, and as with the wafer sort test, ICs that fail to meet the performance standards set by a manufacturer are discarded.
One common parameter that is tested prior to shipping an IC to a customer is the input leakage current. Input leakage current refers to the static current drawn at an input. Normally, this measurement is made using a precision measurement unit (PMU). If any I/O on an IC shows input leakage current in excess of the maximum set by the manufacturer, the IC is discarded. For example, the Virtex™-II FPGA (field programmable gate array) manufactured by Xilinx®, Inc. of San Jose, Calif. has a maximum absolute value input leakage current of 10 μA, as specified on its data sheet, “Virtex™-II Platform FPGAs: DC and Switching Characteristics,” Dec. 6, 2002, page 2, DS031-3 (v2.4) (the “Virtex-II Data Sheet”). Input leakage can be measured by connecting a PMU to an I/O pad of an IC, either at wafer sort or at final test. However, in order to make the current measurement, the PMU must have direct access to each I/O pad to be tested.
Other parameters that are commonly tested include VOL, VOH, IOL, and IOH, and other parameters typically specified on data sheets, and are often governed by requirements of the I/O standards an IC conforms to. VOL is the maximum voltage level that is permitted at an output for a logic low value, and is usually stated with respect to a given current load or logic standard. Similarly, VOH is the minimum voltage level permitted as a logic high. An IC adhering to many different logic and I/O standards can have many different specifications for VOL and VOH. Similarly, IOL and IOH refer to the maximum current that an output must be able to source or sink when driving a logic low or a logic high, respectively. For example, Table 6 at pages 4-5 of the Virtex-II Data Sheet set forth VOL, VOH, IOL, and IOH characteristics for the Virtex-II FPGA. These and other I/O parameters can also be tested by connecting a PMU to an I/O pad either at wafer sort or at final test. The PMU still requires direct access to each I/O pad to be tested in order to test such I/O parameters.
In some applications, however, the probe card used at wafer sort does not have access to every I/O pad of an IC. For example, the tests to be performed at wafer sort may only require access to a subset of the I/O pads. As another example, not all of the final, packaged ICs will make use of every I/O pad on the IC, so it can be more cost effective to touch down only on the common I/O pads that are used by every package configuration. In another example, a manufacturer can choose to run wafer sort tests only through certain I/O pads, since testing costs (such as the costs in aligning and maintaining probe cards) increase as the number of accessed I/O pads increases. However, if only certain I/O pads are accessed, the I/O pads that are not accessed by the tester cannot be tested by a PMU, and the leakage current and other I/O characteristics for those I/O pads cannot be determined.
In cases where not every I/O pad is tested at wafer sort, a manufacturer would test those I/O pads at final test. At final test, all of the I/O pads that are used by an IC in a particular package configuration are connected to package pins, and a manufacturer will typically test all such connected package pins to ensure complete functionality and performance. Testing performance at final test, however, increases the cost to the manufacturer, since the manufacturer still incurs the assembly costs for ICs that fail to meet the input leakage specification or other performance requirements at final test and are rejected and discarded. Had the IC been tested and rejected at the wafer sort test, the manufacturer could have saved at least the cost of assembly.
Therefore, a need exists for a cost-effective method for performing an I/O performance test, wherein such test can be performed early in the fabrication process, such as at wafer sort, and can be performed without having direct access to the I/O pads to be tested.